A team of engineers led by two Indian American professors, both IIT Kharagpur graduates, has developed the first monolithic 3D chip built in a U.S. foundry, delivering the densest 3D chip wiring and order-of-magnitude speed gains.
Subhasish Mitra, the William E. Ayer Professor in Electrical Engineering and professor of computer science at Stanford University, is the principal investigator of a new paper describing the chip presented at the 71st Annual IEEE International Electron Devices Meeting (IEDM).
Tathagata Srimani, assistant professor of electrical and computer engineering at Carnegie Mellon University, is the paper’s senior author, who began the work as a postdoctoral fellow advised by Mitra.
Engineers at Stanford University, Carnegie Mellon University, University of Pennsylvania, and the Massachusetts Institute of Technology collaborated with SkyWater Technology, the largest exclusively U.S.-based pure-play semiconductor foundry, to develop the novel multilayer computer chip whose architecture could help usher in a new era of AI hardware and domestic semiconductor innovation.
Unlike today’s largely flat, 2D chips, the new prototype’s key ultra-thin components rise like stories in a tall building, with vertical wiring acting like numerous high-speed elevators that enable fast, massive data movement.
Its record-setting density of vertical connections and carefully interwoven mix of memory and computing units help the chip bypass the bottlenecks that have long slowed improvement in flat designs. In hardware tests and simulations, the new 3D chip outperforms 2D chips by roughly an order of magnitude.
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While academic labs have previously built experimental 3D chips, this is the first time such a chip has shown clear performance gains and been manufactured in a commercial foundry.
“This opens the door to a new era of chip production and innovation,” said Mitra. “Breakthroughs like this are how we get to the 1,000-fold hardware performance improvements future AI systems will demand.”
Modern AI models, like ChatGPT and Claude, must move staggering amounts of data back and forth between memory, which stores information, and the computing units that process it.
On conventional 2D chips, components sit on a single, flat surface with limited, spread-out memory, so data must travel across a few long, crowded routes. Because the computing elements run much faster than the data can move – and because the chip can’t store enough memory close by – the system ends up constantly waiting on information. Engineers call this bottleneck the “memory wall,” the point at which processing speed outpaces the chip’s ability to deliver data.
For decades, chipmakers addressed the memory wall problem by shrinking transistors – the tiny switches on a chip that perform computations and store data – and squeezing more of them onto each chip. But that strategy, too, is approaching hard, physical limits, which researchers refer to as the “miniaturization wall.”
The new chip climbs these walls by literally rising above them. “By integrating memory and computation vertically, we can move a lot more information much quicker, just as the elevator banks in a high-rise let many residents travel between floors at once,” said Srimani.
Early hardware tests show that the prototype already outperforms comparable 2D chips by roughly a factor of four. Simulations of taller, future versions – with more stacked layers of memory and compute – point to even greater gains.
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Designs with additional tiers show up to a twelve-fold improvement on real AI workloads, including those derived from Meta’s open-source LLaMA model.
Most strikingly, the researchers say the design opens a realistic path to 100- to 1,000-fold improvements in energy-delay product (EDP), a key metric that balances speed and energy efficiency.
By drastically shortening data movement and adding many more vertical pathways, the chip can achieve both higher throughput and lower energy per operation, a combination long viewed as out of reach for conventional, flat architectures.
The researchers emphasize that the long-term significance of this research goes beyond performance. By proving that monolithic 3D chips can be built on U.S. soil, they say, the work establishes a blueprint for a new era of domestic hardware innovation, one in which America can design and manufacture the most advanced chips.
Mitra’s honors include the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur.
Srimani received the SM and the PhD degree in EECS from Massachusetts Institute of Technology and the B.Tech degree in E&ECE from IIT Kharagpur.